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Preliminary
SPR1024A
128Kx8 BITS BUS FLASH
GENERAL DESCRIPTION SPR1024A is a high-performance 1M-bit bus FLASH organized as 128k-byte. With an embedded Bus Memory Interface (BMI) and a Serial interface, SPR1024A allows CPU to access FLASH through 8-bit parallel mode or 1-bit serial mode. To support different access modes of SPDC series CPU, SPR1024A can be defined as 8 Maximum configuration types. With 2.7V to 3.6V power supply voltage, SPR1024A can operate up to 4.0MHz. read current is 1mA and maximum program/erase current is 4mA.
FEATURES 1M-bit (128k x 8 bits) 128 separate pages for erase operation Supply voltage: 2.7V - 3.6V Operating frequency: 4.0MHz Operating current: read 1mA(Max.), program/erase
BLOCK DIAGRAM
MC[1:0] AD[7:0] STATUS ADDRESS CF[4:0] BUS INTERFACE DATA CE, WE, OE COMMAND INTERFACE R,P,E,ME ADDRESS, DATA
DATA
128K x 8 FLASH
ERASE & PROGRAM CONTROLLER
TIMER
4mA(Max) Standby current: 1A (Max.) TTL-compatible I/O Bus memory interface or Serial interface
R,P,E,ME SCK SDA SERIAL INTERFACE
XE,YE, SE,OE, ERASE, PROG, MAS1, NVSTR, IFREN
DATA
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Preliminary
BLOCK DESCRIPTION
SPR1024A
This device contains six components: Bus Interface (BIF), Serial Interface (SIF), Command Interface (CIF), timer, erase & program controller (EPCON) and a 1Mb FLASH. TMODE, ENZ and CF3 - 0 define the CPU types and access modes. When BIF is chosen, MC0 and MC1 act as the Read/Write control signal and AD7 BIF processes these signals and generates chip enable ( CE ), 0 are the bi-directional Address/Data bus.
output enable ( OE ), write enable ( WE ) and FLASH's address in READ mode. generates FLASH's data also. reads from FLASH directly.
In WRITE mode, BIF
CIF interprets signals generated by BIF. If CIF receives READ command, it If CIF receives PROGRAM, ERASE or MASS ERASE, it forwards these But if PROGRAM, ERASE or
commands to EPCON to accomplish them. When SIF is chosen, SCK acts as serial clock and SDA acts as 1-bit serial I/O. If READ command is received, SIF can read from flash directly. MASS ERASE is received, SIF also forwards these commands to EPCON. 200 kHz clock which is provided by the TIMER block shown in block diagram.
BMI DESCRIPTION
When EPCON is active, it needs a
BMI is an interface between SPDC series CPU and its memory. management.
It provides flexible and efficient memory MC0 decides operation
CPU can access up to 4M-bit FLASH via BMI. BMI contains an 8-bits bi-directional
Address/Data bus, AD bus, which is multiplexed by 2 control signals, MC0 and MC1. below:
mode (Read or Write), and MC1 decides AD bus to be address or data bus. MC0 and MC1 decode table list as
MC1
MC0
AD BUS
Bus ROM Power
L L H H
L H L H
Data for Write Data for Read AL AH
Standby Active Standby
The simple timing relation is as follows:
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Preliminary
Read Cycle: MC0 MC1 AD AH AL DATA for read
SPR1024A
Write Cycle: MC0 MC1 AD AH AL DATA for read
According to memory mapping strategy, SPDC series CPUs are classified into two groups. includes SPDC1016, SPDC1064 and SPDC4000 series. Second group includes SPDC256 - 2000.
First group
BMI MEMORY MAPPING FOR SPDC1016, SPDC1064 & SPDC4000
The BMI uses CPU address from 4000h to FFFFh and duplicates some CPU registers in BMI as bank switch to map up to total 4M-bits FLASH. The register usage and mapping table is as below:
Register[bits] Alias Usage
0000 [7:0] 000A[7] 000A[3:0] 000D[1:0] 001A[7]
BSW[7:0] ROA BBS[3:0]
4000-BFFF memory bank switch (8 bits) 4000-BFFF ROM/RAM select (0:ROM / 1:RAM) C000-DFFF BIOS bank switch Volume ID
CVOL0
0: C000-FFFF Volume 0, 1: C000-FFFF depend on Volume select
TYPE A, C, E (ROM)
TYPE B, D, F (RAM)
4000
xrm Xmn xmn xmn xmn 04 00C 014 01C 024
xmn xmn xmn 3F4 3FC 404 xmn xmn xmn 3F6 3FE 406 xmn xmn xmn 3F0 3F8 400 xmn xmn xmn 3F2 3FA 402 0 7E 0 7F 0 80
xmn xmn xrm xrm xrm 7F4 7FC 04 0C 14
xrm xrm 7F4 7FC xrm xrm 7F6 7FE xrm xrm 7F0 7F8 xrm xrm 7F2 7FA 1 FE 1 FF
6000
xrm Xmn xmn xmn xmn 06 00E 016 01E 026
xmn xmn xrm xrm xrm 7F6 7FE 06 0E 16
8000
xmn Xmn xmn xmn xmn 000 008 010 018 020
xmn xmn xrm xrm xrm 7F0 7F8 00 08 10
A000
xmn Xmn xmn xmn xmn 002 00A 012 01A 022
xmn xmn xrm xrm xrm 7F2 7FA 0 FE 0 FF 02 1 00 0A 1 01 12 1 02
ROA BSW
0 00
0 01
0 02
0 03
0 04
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SPR1024A
C000
xmn Xrm xmn xmn xmn xmn xmn xmn xmn xmn xmn xmn xmn xmn xmn xmn 004 06 1 000 002 00C 00E 008 00A 014 016 010 012 01C 01E 018 01A 2 3 4 5 6 7 8 9 A B C D E F
BBS
0
E000
xmn 006
Note1: The blocks of same shadow color are double mapping. Note2: xmn means expanded bus memory. Note3: The size of each block is 128k-bits. Note4: The digit in every block multiplied by 1000 represent the physical address of memory.
For example: C000 xmn 008 BBS = 6 ROA = 0 8000 xmn 008
BSW = 01 That means if CPU accesses to [C000-DFFF when BBS = 6] or [8000-9FFF when ROA = 0 and BSW = 01] (double mapping), BMI will map these address to the physical address 008000-009FFF of FLASH.
BMI MEMORY MAPPING FOR SPDC256-2000
The BMI uses CPU address from 4000h to FFFFh and duplicates some CPU registers in BMI as bank switch to map address. When CPU address is between 4000h to BFFFh, if bank switch is from 00 to 7Fh, then the If Bank switch is from 80h to FFh, then the When CPU address is between C000h to Otherwise, if EXC = 1, it is in expanded mapping address locate in internal ROM which is built in CPU. mapping address locate in expanded memory (FLASH or ROM). FFFFh, If EXC = 0, the mapping address locate in internal ROM. mapping table is as below.
memory, which is double mapped to address from 4000h to 7FFFh at BSW = 80. The register usage and
Register[bits]
Alias
Usage
0000 [7:0] 0007[7] 000B[1] 000D[2:0] 001A[7]
BSW[7:0] MEXT EXC
4000-BFFF memory bank switch (8 bits) 1: bus memory enable 0:C000-FFFF internal, 1:C000-FFFF Volume ID
CVOL0
0: C000-FFFF Volume 0, 1: C000-FFFF depend on Volume select
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SPR1024A
Address 4000 rom 04 6000 rom 06 8000 rom 000 A000 rom 002 BSW 00 rom 00C rom 00E rom 008 rom 00A 01 rom 014 rom 016 rom 010 rom 012 02 rom 01C rom 01E rom 018 rom 01A 03 rom 024 rom 026 rom 020 rom 022 04 rom 3F4 rom 3F6 rom 3F0 rom 3F2 7E rom 3FC rom 3FE rom 3F8 rom 3FA 7F xmn 404 xmn 406 xmn 400 xmn 402 80 xmn 40C xmn 40E xmn 408 xmn 40A 81 xmn 414 xmn 416 xmn 410 xmn 412 82
Type G xmn 424 xmn 426 xmn 420 xmn 422 83 xmn 7F4 xmn 7F6 xmn 7F0 xmn 7F2 FE xmn 7FC xmn 7FE xmn 7F8 xmn 7FA FF
address C000
(Type G) rom/xmn 404
E000
rom/xmn 406
Note1: xmn means expanded bus FLASH. Note2: rom means internal ROM Note3: The digit in every block multiplied by 1000 represent the physical address of FLASH.
ACCESS MODE DESCRIPTION
There're two ways for hardware to identify the local memory and the expanded memory. configuration control signal:
CASCADE MODE (TYPE A, B, C, D, G):
It's defined by the
For SPDC older version CPU and considered only expand to volume 1. (The build in volume ID is fixed to 1 for type C, D, and G)
AD
local memory BFI MEMORY VOLUME 0 Type A,B MC0 MC1
expanded memory BFI MEMORY VOLUME 1 Type C,D,G
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CHIP SELECT MODE (TYPE E, F):
SPR1024A
MC0 is decoded by volume to MC0A, MC0B, and MC0C.
AD local memory BFI MEMORY Type E,F MC0 MC1 MC0A MC0B MC0C expanded memory expanded memory expanded memory BFI MEMORY Type E,F BFI MEMORY Type E,F BFI MEMORY Type E,F
CONFIGURATION MODE SUMMARY CPU Type Decode mode Bank switch CF8-CF3* Volume ID Volume select type
Volume 0 ROA = 0 SPDC1016
00-03 40-43 80-83 7C-7F BC-BF FC-FF 00-03 40-43 80-83 BC-BF FC-FF 00-03 40-43 80-83 BC-BF FC-FF 00-03 40-43 80-83 BC-BF FC-FF
00 01 02 3D 3E 3F 00 01 02 3E 3F 00 01 02 3E 3F 00 01 02 3E 3F
0
0-3 A
0
0-3
0
0-3 B
Volume 0 ROA = 1
0 1
0-3 0-3 C
Volume 1 ROA = 0 SPDC1016 Volume 1 ROA = 1
1 1 0-3 D 1
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CPU Type Decode mode Bank switch CF8-CF3* Volume ID
SPR1024A
Volume select type
ROA=0 SPDC1064 SPDC4000 ROA=1
Chip select
00-03 40-43 80-83 BC-BF FC-FF 00-03 40-43 80-83 BC-BF FC-FF 00-7F 80-83 84-87 FC-FF
00 01 02 3E 3F 00 01 02 3E 3F 0 20 21 3F 1 1
0-3 E
0-3 F
Chip select
Built in SPDC256-2000 Extended ROM Cascade (CI/CO)
0-7 G 0-7
* For the reason to cost down, only 2 bit (CF3 & CF4) is selected to configure the mapping.
CONFIGURATION PINS DEFINE: Type CF2 CF1 CF0
A B C BUS MODE D E F G SERIAL MODE
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
CF3 & CF4 are used to define the starting bank: Type CF4 0 A, B, C, D, E, F 0 1 1 G 1 1 CF3 0 1 0 1 0 1 Bank switch 00-03 (00-3F) 40-43 (40-7F) 80-83 (80-BF) C0-C3 (C0-FF) 80-83 (80-BF) C0-C3 (C0-FF) 00-03 40-43 80-83 F0-F3 04-07 44-47 84-87 F4-F7 Multi-mapping 08-0B 48-4B 88-8B F8-FB 3C-3F 7C-7F BC-BF FC-FF
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Preliminary
BS7 BS6 BS5 BS4 BS3 BS2 BS1
SPR1024A
BS0
CF4
CF3
X
X
X
X
PIN DESCRIPTION Mnemonic PIN No. Type Description
CF4 - 1 CF0 AD7 - 0 MC1 - 0 RESET ENZ VDD VSS SDA SCK TEST NC
16 - 13 19 9-2 21 - 20 22 23 17, 1 11 10 18 12 0
I
Configuration Inputs
I/O I I I I I I/O I I I
Address/Data I/O Control signal Reset Bus Interface/Serial Interface selector Power Supply Ground Serial Interface data I/O Serial Interface Clock TEST MODE No connection
ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Ratings
Supply Voltage to Ground Potential Ambient Operating Temperature Storage Temperature Output Voltage Input Voltage
VDD TA TSTG VOUT VIN
-0.5V~4.5V -10~ 80 -65~150 -0.5V~VDD+0.5V -0.5V~VDD+0.5V
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics.
RECOMMENDED DC OPERATING CONDITIONS (VDD =2.7V - 3.6V, TA = 0 - 70) Characteristics Symbol Limit Min. Typ. Max. Unit
Supply Voltage Supply Voltage Input High Voltage Input Low Voltage
VDD VSS VIH VIL
2.7 0 2.2 -0.3
3.0 0 -
3.6 0 VDD+0.3 0.4
V V V V
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DC ELECTRICAL CHARACTERISTICS (VDD = 2.7 - 3.6V, TA = 0 - 70) Characteristic Symbol Limit Min. Typ. Max. Unit
SPR1024A
Test Condition
Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating Supply Current (f = 4.0MHz), CL = 80pF Standby Current (CMOS)
VOH VOL II(L) IO(L) ICC ISB
2.3 -
-
0.3 1.0 1.0 4.0 1.0
V V
A A
IOH = -1.0mA IOL = 1.0mA
mA
A
MC0 = MC1 = VDD AD[0:7] = VSS
AC OPERATING CHARACTERISTICS (VDD = 2.7 - 3.6V, TA = 0 - 70) for Bus Interface Characteristic Read cycle Symbol Min. Max. Unit
Read cycle period MC0 falling to AH end MC1 falling to MC0 rising MC1 falling to AL end Data latch to MC1 falling MC1 rising to AD Hi-Z
Write Cycle
T tMCAH tM1M0 tMCAL tPM1 tRHZ
250 15 -20 20 -
10 35 35 5.0
ns ns ns ns ns ns
MC0 rising to MC1 rising MC1 rising to AD Hi-Z
tMCW tRHZ
15 15
20 -
ns ns
AC TEST CONDITION
Input Pulse Level Input Rise and Fall Time Input and Output Timing Level Output Load
0.4V to 2.2V 10ns 1.5V CL = 80pF
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TIMING WAVEFORMS FOR BUS INTERFACE READ CYCLE
SPR1024A
CPU_CK tM1M0 T/4 tPM1 T/2 tMCAH AD AH AL tMCAL DATA for READ tRHZ
MC0
MC1
WRITE CYCLE
MC0 T/2 tMCAH tMCAL AL DATA for Write
tMCW
MC1
tWHZ
AD
AH
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ADDRESS MAPPING FOR FLASH CONTROL
SPR1024A
Software command sequence: CPU should write the Volume ID and BANK00 or BBS0A before those command sequences. That will detect which chip is selected. Address in the following table indicates FLASH's physical address. BSW, BBS, and address must be set to the physical address of the FLASH! The BANK00 should be set to
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CF4
CF3
X
X
X
X
BS1
BS0
CF4 & CF3 for selecting starting address (banks)
CF4 - 3 00 01 10 11
Bank (00H)
00-03
40-43
80-83
C0-C3
BANK00[b7:b6] assign to [CF4:CF3]. BANK00[b5:b0] set to the bank which is going to be read, programmed or erased.
Command sequence
Bus cycle 1 Addr
nd
2 data addr
rd
3 data addr
th
4 data Addr
th
5 data
th
6 addr
th
data
S/W ID entry
5555h
AAh
AAAAh
55h
5555h
90h
8000h/ 8001h Any addr.
ID (read) Status
(6)
Read status 5555h Return to normal mode (RESET) XXXX
AAh
AAAAh
55h
5555h
70h
F0h
Main memory
Read Byte program
RA
RD (read) AAh AAh AAh AAAAh AAAAh AAAAh 55h 55h 55h 5555h 5555h 5555h A0h 80h 80h PA
(3)
5555h
PD
(4)
Page Erase 5555h Mass erase 5555h
5555h 5555h
AAh AAh
AAAAh AAAAh
55h 55h
EA
(5)
30h 10h
5555h
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Command sequence Bus cycle 1 Addr
nd
SPR1024A
2 data addr
rd
3 data addr
th
4 data Addr
th
5 data
th
6 addr
th
data
Information block
I-Read I-Byte program
5555h
AAh
AAAAh
55h
5555h
78h
RA
(3)
RD (read) PD
(4)
5555h
AAh AAh AAh
AAAAh AAAAh AAAAh
55h 55h 55h
5555h 5555h 5555h
A8h 88h 88h
PA
Inf. erase(1) 5555h Bmass erase(2) 5555h
5555h 5555h
AAh AAh
AAAAh AAAAh
55h 55h
5555h 5555h
30h 10h
(1) Only erase information block. (2) Erase both main block and information block. (3) PA: program byte address (4) PD: program data (5) EA: page erase address (gray bits in next table) (6) Status: b7 for 0/1: busy/ready, b3 for 0/1: fail/success
PRODUCT IDENTIFICATION TABLE Address Data
Manufacture's code Device code
00000h 00001h
C7h D5h
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ADDRESS SUMMARY Flash ADDR. Main Inform. CPU mapping 4000h - BFFFh
SPR1024A
CPU mapping C000h - DFFFh
CF4 CF3 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Y6 Y5 Y4 Y3 Y2 Y1 Y0 x x x x x x x 0 0 X0 Y6 Y5 Y4 Y3 Y2 Y1 Y0 FA16 FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0
BS7 BS6 BS1 BS0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 BBS3 BBS2 BBS1 BBS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The addresses in gray shadow are page erase addresses.
READ SEQUENCE (MAIN BLOCK)
Start Write volume ID Write bank 00 Read data from address Read completed
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FLASH is already at normal operation These two steps will detect which chip is selected
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READ SEQUENCE (INFORMATION BLOCK)
SPR1024A
Start
FLASH is already at normal operation
Write volume ID These two steps will detect which chip is selected Write bank 00
Write data AAh to address 5555h
Write data 55h to address AAAAh
Enter read-information-block mode
Write data 78h to address 5555h
Read data from address No
End of reading? Yes Read completed
Write F0h to any address
Return to normal mode
Exit from information block
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BYTE PROGRAM SEQUENCE
SPR1024A
Start
FLASH is already at normal operation
Write volume ID Write bank 00
These two steps will detect which chip is selected
Write data AAh to address 5555h Enter program-main-block mode Write A8h to 5555h will enter program-information-block mode
Write data 55h to address AAAAh Write data A0h to address 5555h
Program data to address Enter status-polling mode FLASH accept no command (including reset) when it's busy. Read any byte
No
Bit7=1? Bit3=1? Yes Program completed
Detect end of programming or fail Ready status: accept reset only Program time: 85us ~ 170us Exit from status-polling
Write F0h to any address Return to normal mode
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PAGE ERASE SEQUENCE
SPR1024A
Start
FLASH is already at normal operation
Write volume ID These two steps will detect which chip is selected Write bank 00
Write data AAh to address 5555h
Enter page-erase mode
Write data 55h to address AAAAh Write 88h to 5555h will enter information-block-erase mode
Write data 80h to address 5555h
Write data AAh to address 5555h Write data 55h to address AAAAh
Write data 30h to page address (EA) which is going to be erased
Read any byte
Enter status-polling mode FLASH accept no command (including reset) when it's busy.
No
Bit7=1? Bit3=1? Yes Erase completed
Detect end of erase
Ready status: accept reset only Erase time: 10.5ms ~ 13.5ms Exit from status-polling
Write F0h to any address
Return to normal mode
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MASS ERASE SEQUENCE
SPR1024A
Start Write volume ID
FLASH is already at normal operation
These two steps will detect which chip is selected Write bank 00
Write data AAh to address 5555h Write data 55h to address AAAAh
Enter mass-erase mode
Write data 80h to address 5555h
Write 88h to 5555h will mass-erase both information & main block
Write data AAh to address 5555h Write data 55h to address AAAAh
Write data 10h to address 5555h
Read any byte No
Enter status-polling mode FLASH accept no command (including reset) when it's busy.
Bit7=1? Bit3=1? Yes Erase completed
Detect end of erase
Ready status: accept reset only Erase time: 10.5ms ~ 13.5ms Exit from status-polling
Write F0h to any address
Return to normal mode
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ENTER STATUS-POLLING MODE FROM NORMAL MODE
SPR1024A
Start Write volume ID
FLASH is already at normal operation
These two steps will detect which chip is selected Write bank 00
Write data AAh to address 5555h Write data 55h to address AAAAh Write data 70h to address 5555h Enter status-polling mode
Read data from address No
Enter status-polling mode FLASH accept no command but reset
End of reading? Yes FLASH is ready Write F0h to any address Exit from status polling
Return to normal mode
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ERASE ALGORITHM FOR IMPROVING ENDURANCE PERFORMANCE Start FLASH is already at normal operation
SPR1024A
ERASE procedure (page, mass or information block erase)
Erase time = 10.5ms ~ 13.5ms
No
Verify the entire memory array to be FFh or not
Yes ERASE procedure Add 1 phase after verify erase OK
Erase completed
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SERIAL INTERFACE BIT TRANSFER
SPR1024A
One clock pulse is generated for each data bit transferred. The data on SDA line must be stable during the HIGH period of clock. The HIGH or LOW states of the data line can only change when the clock signal on the SCK line is LOW.
SCK SDA data line stable; change of data allowed data valid
Within the procedure of the SPSI serial interface, unique situations arise which are defined as START (S) and STOP (P) conditions. A HIGH to LOW transition on SDA line while SCK is HIGH indicates a START condition. A LOW to HIGH transition on SDA line while SCK is HIGH defines a STOP condition.
SCK SDA START condition (S) STOP condition (P)
INSTRUCTION SET
(1) Main block READ with random address access: Main block READ command is a start bit followed by an 8-bit opcode (A[24:17]=10000000) and a 17-bit address (A[16:0]). After receiving main block READ command, the SDA line should be set to the SPR1024A will begin shifting out the data addressed (MSB first) on the falling edge After 8 data bits high-impedance state.
of the SCK clock and the output data bit will be stable after the specified time delay (tACC). are shifted out, a stop bit is needed to terminate the command. Start bit S 10000000 A16 - A0 Stop bit D7 - D0 P
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(2) Main block READ with auto-address-count:
SPR1024A
Main block READ with auto-address-count command is the same as main block READ except that after first 8 data bits are shifted out, no stop bit is inserted before the next SCK falling edge. followed. Start bit S 10000000 A16 - A0 D7 - D0 addr D7 - D0 addr+1 The procedure will continue until a stop bit is received. Stop bit D7 - D0 addr+n P SPR1024A will automatically increase the address by 1 and its data content will be shifted out by the clock cycle that
(3) Main block BYTE PROGRAM: Main block BYTE PROGRAM command is a start bit followed by an 8-bit opcode (A[24:17]=00000000), a 17-bit address (A[16:0]) and an 8-bit data (D[7:0]). command. Start bit S 00000000 A16 - A0 Stop bit D7 - D0 P After receiving main block BYTE PROGRAM command, Then, a stop bit terminates the a specified interval (tPGM) is needed to program data into the FLASH.
(4) Main block PAGE ERASE: Main block PAGE ERASE command is a start bit followed by an 8-bit opcode (A[24:17]=01000000) and a 17-bit address (A[16:0]). CARE. A16 to A10 are used to select which page to be erased. A9 to A0 are DON'T After receiving main block PAGE ERASE command, a specified interval (tERASE) is needed to erase
the selected page of the FLASH. Then, a stop bit terminates the command. Start bit S 01000000 Stop bit A16 - A0 P
(5) Main block MASS ERASE: Main block MASS ERASE command is a start bit followed by an 8-bit opcode (A[24:17]=01100000) and a 17-bit address (A[16:0]). terminates the command. Start bit S 01100000 Stop bit A16 - A0 P
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A16 to A0 are DON'T CARE.
After receiving main block MASS ERASE Then, a stop bit
command, a specified interval (tERASE) is needed to erase the main block of the FLASH.
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(6) Information block READ:
SPR1024A
The command is the same as main block READ except the opcode changes to (10010000) and the active region changes to information block. Start bit S 10010000 A16 - A0 Stop bit D7 - D0 P
(7) Information block READ with auto-address-count: The command is the same as main block READ with auto-count except the opcode changes to (10010000) and the active region changes to information block. Start bit S 10010000 A16 - A0 D7 - D0 addr D7 - D0 addr+1 Stop bit D7 - D0 addr+n P
(8) Information block BYTE PROGRAM: The command is the same as main block BYTE PROGRAM except the opcode changes to (00010000) and the active region changes to information block. Start bit S 00010000 A16 - A0 Stop bit D7 - D0 P
(9) Information block PAGE ERASE: The command is the same as main block PAGE ERASE except the opcode changes to (01010000) and the active region changes to information block. There is only one page in information block. All of the bits in information block are erased at the same time. Start bit S 01010000 Stop bit A16 - A0 P
(10) Both blocks MASS ERASE: The command is the same as main block MASS ERASE except the opcode changes to (01110000) and both main block and information block will be erased. Start bit S 01110000 Stop bit A16 - A0 P
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Preliminary
AC CHARACTERISTICS Characteristic (VDD = 2.7 - 3.6V, TA = 0 - 70) Symbol Max. Min.
SPR1024A
Unit
Period of SCL Low period of SCL clock High period of SCL clock Address setup time Address hold time READ access time READ data hold time PROGRAM data setup time PROGRAM data hold time PROGRAM time ERASE time Rise time of SCL Fall time of SCL Rise time of SDA Fall time of SDA
tC tLOW tHIGH tAS tAH tACC tDH tPDS tPDH tPGM tERASE tRSC tFCL tRDA tFDa
100 15 15 15 15
400 170 170 100 20 20 100 20 125 13.5 -
ns ns ns ns ns ns ns ns ns us ms ns ns ns ns
READ COMMAND
SCK tACC SDA
A24 A23 A0 D7 D6 D5 D4 D3 D2 D1 D0
tDH
start
stop
READ COMMAND WITH AUTO-ADDRESS-COUNT
tC SCK tAS SDA
A24 A23
tHIGH tAH
A0 D7 D6 D0 D7
tLOW
D0 D7
D0 D7
D0
start
addr
addr+1
addr+n
stop
Sunplus Technology Co., Ltd.
23
Rev.: 0.1
2000.11.17
Preliminary
PROGRAM COMMAND
tPGM SCK tPDS SDA
A24A23
SPR1024A
tPDH D0 stop
A0 D7 D6
start
PAGE ERASE AND MASS ERASE COMMAND tERASE
A24 A23
A2 A1 A0
start
stop
Sunplus Technology Co., Ltd.
24
Rev.: 0.1
2000.11.17
Preliminary
PAD ASSIGNMENT AND LOCATIONS PAD ASSIGNMENT
SPR1024A
23
RESET 22
21
20
19
18
17
16
15
14
13 SDA 10 CF1
VDD
Chip Size: 1590m x 3110m This IC substrate should be connected to VSS
Note: To ensure that the IC functions properly, please bond all of VDD and VSS pins.
Ordering Information Product Number Package Type
SPR1024A-nnnnV-C
Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z).
11
0
1
2
3
4
5
6
7
8
9
VSS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
NC
TEST
MC0
VDD
MC1
SCK
ENZ
CF4
CF3
CF0
CF2
12
Chip form
NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance to supply the best possible product.
Sunplus Technology Co., Ltd.
25
Rev.: 0.1
2000.11.17
Preliminary
PAD LOCATIONS Pad No Pad Name X
SPR1024A
Y
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
NC VDD AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 SDA VSS TEST CF1 CF2 CF3 CF4 VDD SCK CF0 MC0 MC1 RESET ENZ
-718 -559 -439 -319 -199 -79 41 161 281 401 521 641 635 515 395 275 155 35 -85 -205 -325 -445 -565 -685
-1455 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 -1445 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444
Note: When bus interface is selected: ENZ, SDA, SCK -> GND, TEST -> NC When serial interface is selected: AD[7:0], CF[4:3], MC[1:0] -> GND, CF[2:0], ENZ -> VDD, TEST -> NC
Sunplus Technology Co., Ltd.
26
Rev.: 0.1
2000.11.17
Preliminary
DISCLAIMER
SPR1024A
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. document are for reference purposes only. Please note that application circuits illustrated in this
Sunplus Technology Co., Ltd.
27
Rev.: 0.1
2000.11.17

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